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ST8024
Smartcard interface
General features

Designed to be compatible with the NDS conditional access system IC card interface 3 or 5V supply for the IC (VDD and GND) Three specifically protected half-duplex bidirectional buffered I/O lines to card contacts C4, C7 and C8 DC/DC converter for VCC generation separately powered from a 5 V 20% supply (VDDP AND PGND) 3 or 5V 5% regulated card supply voltage (VCC) with appropriate decoupling has the following capabilities: - ICC < 80mA at VDDP = 4 to 6.5V - Handles current spikes of 40nA up to 20MHz - Controls rise and fall times - Filtered overload detection at approximately 120mA Thermal and short-circuit protection on all card contacts Automatic activation and deactivation sequences; initiated by software or by hardware in the event of a short-circuit, card take-off, overheating, VDD or VDDP drop-out Enhanced ESD protection on card side (>6 kV) 26MHz integrated crystal oscillator Clock generation for cards up to 20MHz (divided by 1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals) with synchronous frequency changes

SO-28
TSSOP28
Non-inverted control of RST via pin RSTIN ISO 7816, GSM11.11 and EMV (payment systems) compatibility Supply supervisor for spike-killing during power-on and power-off and power-on reset (threshold fixed internally or externally by a resistor bridge) Built-in debounce on card presence contacts One multiplexed status signal off

Description
The ST8024 is a complete low cost analog interface for asynchronous 3V and 5V smart cards. It can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. ST8024 is a direct replacement of ST8004. Main applications are: smartcard readers for Set Top Box, IC card readers for banking, identification, Pay TV.

Order codes
Part number ST8024CDR ST8024CTR December 2006 Temperature range -25 to 85 C -25 to 85 C Package SO-28 (Tape & Reel) TSSOP28 (Tape & Reel) Rev 6 Packaging 1000 parts per reel 1000 parts per reel 1/30
www.st.com
30
Contents
ST8024
Contents
1 2 3 4 5 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 5.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.1 5.2.2 5.2.3 Without external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 14 With an external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 15 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10
Clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I/O Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VCC Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 7 8
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/30
ST8024
Diagram
1
Figure 1.
Diagram
Block diagram
3/30
Pin configuration
ST8024
2
Figure 2.
Pin configuration
Pin connections
Table 1.
Pin N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4/30
Pin description
Symbol CLKDIV1 CLKDIV2 5V/3V PGND C1+ VDDP C1VUP PRES PRES I/O AUX2 AUX1 CGND CLK RST VCC VTHSEL CMDVCC Control of CLK Frequency Control of CLK Frequency VCC selection pin. Power Ground for Step-Up converter External Cap. for Step-Up converter Power Supply for Step-Up converter External Cap. Step-Up converter Output of Step-Up converter Card Presence Input (Active Low) Card Presence Input (Active High) Data Line to and from card (C7) (internal 11k pull-up resistor connected to VCC) Auxiliary line to and from card (C8) (internal 11k pull-up resistor connected to VCC) Auxiliary line to and from card (C4) (internal 11k pull-up resistor connected to VCC) Ground for card signal (C5) Clock to card (C3) Card Reset (C2) Supply Voltage for the card (C1) Deactivation threshold selector pin (under voltage lock-out) Start activation sequence input (Active Low) Name and function
ST8024 Table 1.
Pin N 20 21 22 23 24 25 26 27 28
Pin configuration Pin description
Symbol RSTIN VDD GND OFF XTAL1 XTAL2 I/OUC AUX1UC AUX2UC Card Reset Input from MCU Supply Voltage Ground Interrupt to MCU (active Low) Crystal or external clock input Crystal connection (leave this pin open if external clock is used) MCU data I/O line (internal 11k pull-up resistor connected to VDD) Non-inverting Receiver Input (internal 11k pull-up resistor connected to VDD) Non-inverting Receiver Input (internal 11k pull-up resistor connected to VDD) Name and function
5/30
Maximum ratings
ST8024
3
Table 2.
Symbol
Maximum ratings
Absolute maximum ratings
Parameter Min -0.3 -0.3 -0.3 Max 7 VDD + 0.3 VCC + 0.3 7 -6 -2 6 2 150 -40 150 Unit V V V V kV kV C C
VDD, VDDP Supply Voltage Vn1 Vn2 Vn3 ESD1 ESD2 TJ(MAX) TSTG Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2, PORADJ, CMDVCC, PRES, PRES and OFF Voltage on card contact pins I/O, RST, AUX1, AUX2 and CLK Voltage on pins VUP, S1 and S2 MIL-STD-883 class 3 on card contact pins, PRES and PRES (Note: 1, 2) MIL-STD-883 class 2 on C contact pins and RSTIN (Note 1, 2) Maximum Operating Junction Temperature Storage Temperature Range
Note: Note: 1 2
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All card contacts are protected against any short with any other card contact. Method 3015 (HBM, 1500 , 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground.
Thermal data
Parameter Thermal resistance junction-ambient temperature Condition Multilayer test board (Jedec standard) SO-28 56 TSSOP28 50 Unit K/W
Table 3.
Symbol RthJA
Table 4.
Symbol TA
Recommended operating conditions
Parameter Temperature range Test Conditions Min. -25 Typ. Max. 85 Unit C
6/30
ST8024
Electrical characteristics
4
Table 5.
Symbol VDD VDDP
Electrical characteristics
Electrical characteristics over recommended operating condition (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Supply voltage Supply voltage for the voltage doubler Supply current Card Active; fCLK = fXTAL; CL = 30pF Inactive mode DC/DC converter supply current Active mode; fCLK = fXTAL; CL = 30pF; |ICC| =0 VCC = 5V; |ICC| = 80 mA VCC = 3V; |ICC| = 65 mA Vth2 VHYS2 Falling threshold voltage on VDD Hysteresis of threshold voltage Vth2 External rising threshold voltage on VDD no external resistors at pin PORADJ; VDD level falling no external resistors at pin PORADJ external resistor bridge at pin PORADJ; VDD level rising 2.35 50 1.25 1.19 30 2.45 100 1.28 1.22 60 1.5 0.1 10 mA 200 100 2.55 150 1.31 1.25 90 V mV V V mV VCC = 5V; |ICC| < 80 mA VCC = 5V; |ICC| < 20 mA Card Inactive IDD Test Conditions Min. 2.7 4.0 3.0 5 Typ. Max. 6.5 6.5 V 6.5 1.2 mA Unit V
IDDP
Vth(ext)rise Vth(ext)fall VHYS(ext)
External falling threshold external resistor bridge at pin PORADJ; voltage on VDD VDD level falling Hysteresis of threshold voltage Vth(ext) external resistor bridge at pin PORADJ
Hysteresis of threshold VHYS(ext) voltage Vth(ext) variation with temperature tW Width of internal PowerOn reset pulse Leakage current on pin PORADJ Total power dissipation
external resistor bridge at pin PORADJ no external resistor at pin PORADJ external resistor bridge at pin PORADJ VPORADJ < 0.5 V VPORADJ > 1.0 V Continuous operation; Ta = -25 to 85C 4 8 -0.1 -1 8 16 4
0.25 12
mV/K
ms 24 10 A 1 0.56 W
IL PTOT
7/30
Electrical characteristics
ST8024
Table 6.
Symbol fCLK
Step-up Converter (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25C)
Parameter Clock Frequency Card active Test Conditions Min. 2.2 5.2 3.8 5.2 3.5 5.8 4.1 5.7 3.9 Typ. Max. 3.2 6.2 V 4.4 6.2 V 4.3 Unit MHz
Threshold voltage for Step- 5 V card Vth(vd-vf) up Converter to change to 3 V card voltage follower VUP(av) Output Voltage on pin VUP VCC = 5 V (average value) VCC = 3 V; VDDP = 3.3 V
Table 7.
Symbol CVCC
Card supply voltage characteristics (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C) (Note 1)
Parameter External capacitance on pin VCC Test Conditions Min. 80 -0.1 -0.1 4.75 2.85 4.65 2.76 4.65 2.76 4.65 2.76 0 0 5 3 5 3 5 3 5 3 Typ. Max. 220 0.1 0.3 5.25 3.15 5.25 V 3.20 5.25 3.20 5.25 3.20 350 80 65 90 0.08 0.15 120 0.22 V/s mA mV Unit nF
Note 2 and Note 3
Card Inactive; |ICC| = 0 mA 5 and 3V card Card Inactive; |ICC| = 1 mA 5 and 3V card Card Active; |ICC| < 80 mA Card Active; |ICC| < 65 mA 5 V card 3 V card 5 V card
VCC
Card supply voltage (including ripple voltage)
Card Active; single current pulse IP =-100 mA; tp=2 s
Card Active; single current 3 V card pulse IP =-100 mA; tp =2 s Card active; current pulses, 5 V card QP = 40 nAs 3 V card Card Active; current pulses 5 V card QP =40 nAs with |ICC| < 200mA, tp < 400 ns 3 V card
VCC
(RIPPLE) (P-P)
Ripple voltage on VCC (Peak to Peak value)
fRIPPLE = 20 KHz to 200 MHz VCC = 0 to 5V
|ICC|
Card supply current
VCC = 0 to 3V VCC short circuit to GND
SR
Slew rate
Slew up or down
8/30
ST8024
Electrical characteristics
Table 8.
Symbol CXTAL1,2 fXTAL fXTAL1 VIH VIL
Crystal connection (pins XTAL1 and XTAL2) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter External capacitance on pins XTAIL1, XTAIL2 Crystal Frequency Frequency applied on pin XTAL1 High level input voltage on pin XTAIL1 Low level input voltage on pin XTAIL1 Test Conditions Depends on type of crystal or resonator used 2 0 0.7 VDD -0.3 Min. Typ. Max. 15 26 26 VDD+0.3 +0.3VDD Unit pF MHz MHz V V
Table 9.
Symbol
Data Lines (PINS I/O, I/OUC, AUX1, AUX2, AUX1UC AND AUX2UC) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Test Conditions Min. Typ. Max. 200 100 1 10 Unit ns ns MHz pF
tD(I/O-I/OUC), I/O to I/OUC, I/OUC to I/O falling edge tD(I/OUC-I/O) delay tpu fI/O(MAX) CI Active pull-up pulse width Maximum frequency on data lines Input capacitance on data lines
Table 10.
Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated 11k Pull-up resistor to VCC (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Test Conditions NO LOAD Inactive mode IO(inactive)=1mA Inactive mode; pin grounded No DC Load 0.9 VCC 0.75 VCC 0 0 VCC-0.4 1.5 0.3 VIH = VCC VIL = 0 V Pull-up resistor to VCC 9 11 0.3 -1 VCC+0.1 VCC+0.1 0.4 0.2 V VCC VCC+0.3 0.8 10 600 13 V V A A k 9/30 V mA Min. 0 Typ. Max. 0.1 V Unit
Symbol
VO(inactive) Output Voltage IO(inactive) Output Current
VOH
High Level Output Voltage
5 and 3 V cards; IOH < - 40A |IOH| 10mA
VOL VIH VIL |ILIH| |IIL| RPU
Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Current Integrated pull-up resistor
IOL = 1 mA IOL 15 mA
Electrical characteristics Table 10.
ST8024
Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated 11k Pull-up resistor to VCC (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Data Input transition time Data Output transition time Current when pull-up active Test Conditions VIL max to VIH min VO = 0 to VCC; CL 80 pF; 10% to 90% VOH = 0.9VCC; CL = 80 pF -1 Min. Typ. Max. 1.2 0.1 Unit s s mA
Symbol tT(DI) tT(DO) IPU
Table 11.
Data lines to microcontroller (pins I/OUC, AUX1UC AND AUX2UC with integrated 11k Pull-up resistor to VDD (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Current VIH = VDD VIL = 0 V 9 11 Test Conditions 5 and 3 V card; IOH < -40A No DC Load IOL = 1 mA Min. 0.75 VDD 0.9 VDD 0 0.7 VDD -0.3 Typ. Max. VDD+0.1 VDD+0.1 0.3 VDD+0.3 0.3 VDD 10 600 13 1.2 0.1 -1 V V V A A k s s mA Unit V
Symbol VOH VOL VIH VIL |ILIH| |IL| RPU tT(DI) tT(DO) IPU
Internal pull-up resistance to Pull-up resistor to VDD VDD Data Input transition time Data Output transition time Current when pull-up active VIL(max) to VIH(min) VO = 0 to VDD; CL < 30 pF; 10% to 90% VOH = 0.9VDD; CL = 30 pF
Table 12.
Symbol fOSC(INT)
Internal oscillator (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted.Typical values are to TA = 25C)
Parameter Frequency of internal oscillator Active mode 2.2 2.7 3.2 MHz Test Conditions Inactive mode Min. 55 Typ. 140 Max. 200 Unit kHz
10/30
ST8024
Electrical characteristics
Table 13.
Symbol VO(inactive) IO(inactive)
Reset output to card reader (pin RST) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Output Voltage in Inactive Mode Output Current Test Conditions IO(inactive) = 1 mA No Load Inactive mode; pin grounded RST Enable IOL = 200 A IOL = 20 mA (current limit) High Level Output Voltage Rise and fall time IOH = -200 A IOH = -20 mA (current limit) CL = 100 pF; VCC = 5 or 3 V 0 VCC-0.4 0.9VCC 0 Min. 0 0 0 Typ. Max. 0.3 V 0.1 -1 2 0.2 V VCC VCC 0.4 0.1 s V mA s Unit
tD(RSTIN-RST) RSTN to RST Delay VOL Low Level Output Voltage
VOH tR, tF
Table 14.
Symbol VO(inactive) IO(inactive)
Clock output to card reader (pin CLK) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Output voltage in inactive mode Test Conditions IO(inactive) = 1 mA No Load Output current CLK Inactive mode; pin grounded IOL = 200 A Min. 0 0 0 0 VCC-0.4 0.9VCC 0 Typ. Max. 0.3 V 0.1 -1 0.3 V VCC VCC V 0.4 16 45 0.2 55 ns % V/ns mA Unit
VOL
Low level output voltage
IOL = 70 mA (current limit) IOH = -200 A
VOH tR, tF SR
High level output voltage
IOH = -70 mA (current limit) CL = 30 pF (Note 4) CL = 30 pF (Note 4) Slew up or down; CL = 30 pF
Rise and fall time Duty factor (except for fXTALS) Slew rate
11/30
Electrical characteristics
ST8024
Table 15.
Control inputs (PINS CLKDIV1, CLKDIV2, CMDVCC, RSTIN AND 5V/3V (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C) (Note 5)
Parameter Input voltage LOW Input voltage HIGH Input leakage current HIGH Input leakage current LOW VIH = VDD VIL = 0 Test Conditions Min. -0.3 0.7VDD Typ. Max. 0.3VDD VDD 1 1 Unit V V A A
Symbol VIL VIH |ILIH| |ILIL|
Table 16.
Card presence inputs (PINS PRES AND PRES) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25C) (Note 6)
Parameter Input Voltage LOW Input Voltage HIGH Input Leakage Current HIGH VIH = VDD Test Conditions Min. -0.3 0.7 VDD Typ. Max. 0.3 VDD VDD+0.3 5 5 Unit V V A A
Symbol VIL VIH |ILIH| |ILIL|
Input Leakage Current LOW VIL = 0
Table 17.
Interrupt Output (PIN OFF NMOS Drain With Integrated 20 k PULL-UP Resistor To VDD); (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25C)
Parameter Low Level Output Voltage High Level Output Voltage Integrated pull-up resistor Test Conditions IOL = 2 mA IOH = -15 A 20k Pull-up resistor to VDD Min. 0 0.75 VDD 16 20 24 Typ. Max. 0.3 Unit V V k
Symbol VOL VOH RPU
Table 18.
Symbol |ICC(SD)| II/O(lim)
Protection And Limitation (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Shutdown and limitation current pin VCC limitation current pins I/O, AUX1 and AUX2 Test Conditions Min. 90 -15 -70 -20 150 Typ. Max. 120 15 70 20 Unit mA mA mA mA C
ICLK(lim) limitation current pin CLK IRST(lim) limitation current pin RST TSD Shut down temperature
12/30
ST8024
Electrical characteristics
Table 19.
Symbol tACT tDE t3 t5 tdebounce
Timing (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Activation time Deactivation time Test Conditions (See Figure 5.) (See Figure 7.) 60 Min. Typ. 180 80 Max. 220 100 130 140 140 Unit s s s s s
Start of the windows for sending (See Figure 6.) CLK to card End of the windows for sending CLK to card Debounce time pins PRES and PRES (See Figure 6.) (See Figure 8.)
Note:
1
All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is specified as a function of VDD or VCC it means their actual value at the moment of measurement. To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Figure 10.). Permitted capacitor values are 100 + 100 nF, or 220 nF. Transition time and duty factor definitions are shown in Figure 3.; = t1/(t1+ t2). Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 19. Pin PRES is active LOW; pin PRES is active HIGH see Figure 8. and Figure 9.; PRES has an integrated 1.25 A current source to GND. (PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active.
Figure 3. Definition of output and input transition times
2 3 4 5 6
13/30
Functional description
ST8024
5
Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816 terminology.
5.1
Power supply
The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All signals interfacing with the system controller are referred to VDD, therefore VDD should also supply the system controller. All card reader contacts remain inactive during power-on or power-off. The internal circuits are maintained in the reset state until VDD reaches Vth2 +Vhys2 and for the duration of the internal Power-on reset pulse, tW (see Figure 4.). When VDD falls below Vth2, an automatic deactivation of the contacts is performed. A DC/DC converter is incorporated to generate the 5 or 3 V card supply voltage (VCC). The DC/DC converter should be supplied separately by VDDP and PGND. Due to the possibility of large transient currents, the two 100 nF capacitors of the DC/DC converter should be located as near as possible to the IC and have an ESR less than 100 m . The DC/DC converter functions as a voltage doubler or a voltage follower according to the respective values of VCC and VDDP (both have thresholds with a hysteresis of 100 mV). The DC/DC converter function changes as follows: VCC = 5 V and VDDP > 5.8 V; voltage follower VCC = 5 V and VDDP < 5.7 V; voltage doubler VCC = 3 V and VDDP > 4.1 V; voltage follower VCC = 3 V and VDDP < 4.0 V; voltage doubler. Supply voltages VDD and VDDP may be applied to the IC in any sequence. After powering the device, OFF remains LOW until CMDVCC is set HIGH. During power off, OFF falls LOW when VDD is below the falling threshold voltage.
5.2
5.2.1
Voltage supervisor
Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8ms (tW) is used internally to keep the IC inactive during power-on or power-off of the VDD supply (see Figure 4.). As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the command lines. This state also lasts for the duration of tW after VDD has reached a level higher than Vth2 + Vhys2. When VDD falls below Vth2, a deactivation sequence of the contacts is performed.
14/30
ST8024 Figure 4. Voltage supervisor
Functional description
5.2.2
With an external divider on pin PORADJ
If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Figure 1.), then the following occurs: - The internal threshold voltage Vth2 is overridden by the external voltage and by the hysteresis, therefore: Vth2(ext)(rise) = (1 + R1/R2) x (Vbridge + Vhys(ext)/2) Vth2(ext)(fall) = (1 + R1/R2) x (Vbridge - Vhys(ext)/2) where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ. - The reset pulse width tW is doubled to approximately 16 ms. Input PORADJ is biased internally with a pull-down current source of 4 A which is removed when the voltage on pin PORADJ exceeds 1 V. This ensures that after detection of the external bridge by the IC during power-on, the input current on pin PORADJ does not cause inaccuracy of the bridge voltage. The minimum threshold voltage should be higher than 2 V. The maximum threshold voltage may be up to VDD.
5.2.3
Application examples
The voltage supervisor is used as Power-on reset and as supply dropout detection during a card session. Supply dropout detection is to ensure that a proper deactivation sequence is followed before the voltage is too low. For the internal voltage supervisor to function, the system microcontroller should operate down to 2.35 V to ensure a proper deactivation sequence. If this is not possible, external resistor values can be chosen to overcome the problem.
5.3
Clock circuitry
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2. The clock frequency can be fXTAL, 1/2 x fXTAL, 1/4 x fXTAL or 1/8 x fXTAL. Frequency selection is made via inputs CLKDIV1 and CLKDIV2 (see Table 20).
15/30
Functional description
ST8024
Table 20.
Clock frequency selection (1)
CLKDIV1 0 0 1 1 CLKDIV2 0 1 1 0 fCLK fXTAL/8 fXTAL/4 fXTAL/2 fXTAL
1. The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that during transition no pulse is shorter than 45% of the smallest period, and that the first and last clock pulses about the instant of change have the correct width. When changing the frequency dynamically, the change is effective for only eight periods of XTAL1 after the command. The duty factor of fXTAL depends on the signal present at pin XTAL1. In order to reach a 45 to 55% duty factor on pin CLK, the input signal on pin XTAL1 should have a duty factor of 48 to 52% and transition times of less than 5% of the input signal period. If a crystal is used, the duty factor on pin CLK may be 45 to 55% depending on the circuit layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin CLK is guaranteed between 45 and 55% of the clock period. The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used, or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as shown in the activation sequences shown in Figure 5. and Figure 6. If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse will be applied to the card when it is sent by the system microcontroller (after completion of the activation sequence).
5.4
I/O Transceivers
The three data lines I/O, AUX1 and AUX2 are identical.The idle state is realized by both I/O and I/OUC lines being pulled HIGH via a 11 k resistor (I/O to VCC and I/OUC to VDD). Pin I/O is referenced to VCC, and pin I/OUC to VDD, thus allowing operation when VCC is not equal to VDD. The first side of the transceiver to receive a falling edge becomes the master. An anti-latch circuit disables the detection of falling edges on the line of the other side, which then becomes a slave. After a time delay td(edge), an N transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side. When the master side returns to logic 1, a P transistor on the slave side is turned on during the time delay tpu and then both sides return to their idle states. This active pull-up feature ensures fast LOW-to-HIGH transitions; it is able to deliver more than 1 mA at an output voltage of up to 0.9 VCC into an 80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the internal pull-up resistor and the load current. The current to and from the card I/O lines is limited internally to 15 mA and the maximum frequency on these lines is 1 MHz.
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ST8024
Functional description
5.5
Inactive mode
After a Power-on reset, the circuit enters the inactive mode. A minimum number of circuits are active while waiting for the microcontroller to start a session: - All card contacts are inactive (approximately 200 to GND) - Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 k pull-up resistor to VDD) - Voltage generators are stopped - XTAL oscillator is running - Voltage supervisor is active - The internal oscillator is running at its low frequency.
5.6
Activation sequence
After power-on and after the internal pulse width delay, the system microcontroller can check the presence of a card using the signals OFF and CMDVCC as shown in Table 21. If the card is in the reader (this is the case if PRES or PRES is active), the system microcontroller can start a card session by pulling CMDVCC LOW. The following sequence then occurs (see Figure 6.): 1. CMDVCC is pulled LOW and the internal oscillator changes to its high frequency (t0). 2. The voltage doubler is started (between t0 and t1). 3. VCC rises from 0 to 5 V (or 3 V) with a controlled slope (t2 = t1 + 1.5 x T) where T is 64 times the period of the internal oscillator (approximately 25 s). 4. I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T) (these were pulled LOW until this moment). 5. CLK is applied to the C3 contact of the card reader (t4). 6. RST is enabled (t5 = t1 + 7T). The clock may be applied to the card using the following sequence (see Fig.5): 1. Set RSTIN HIGH. 2. Set CMDVCC LOW. 3. Reset RSTIN LOW between t3 and t5; CLK will start at this moment. 4. RST remains LOW until t5, when RST is enabled to be the copy of RSTIN. 5. After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK pulses before toggling RST. If the applied clock is not needed, then CMDVCC may be set LOW with RSTIN LOW. In this case, CLK will start at t3 (minimum 200 ns after the transition on I/O), and after t5, RSTIN may be set HIGH in order to obtain an Answer To Request (ATR) from the card. Activation should not be performed with RSTIN held permanently HIGH Table 21. Card presence indicator
OFF H L CMDVCC H H Indication card present card not present
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Functional description Figure 5. Activation sequence using RSTIN and CMDVCC
ST8024
Figure 6.
Activation sequence at t3
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ST8024
Functional description
5.7
Active mode
When the activation sequence is completed, the ST8024 will be in its active mode. Data are exchanged between the card and the microcontroller via the I/O lines. The ST8024 is designed for cards without VPP (the voltage required to program or erase the internal non-volatile memory).
5.8
Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit then executes an automatic deactivation sequence by counting the sequencer back and finishing in the inactive mode (see Figure 7.): 1. RST goes LOW (t10). 2. CLK is held LOW (t12 = t10 + 0.5 x T) where T is 64 times the period of the internal oscillator (approximately 25 s). 3. I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T). 4. VCC starts to fall towards zero (t14 = t10 + 1.5 x T). 5. The deactivation sequence is complete at tde, when VCC reaches its inactive state. 6. VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND; I/OUC, AUX1UC and AUX2UC remain at VDD (pulled-up via a 11 k resistor). 7. The internal oscillator returns to its lower frequency. Figure 7. Deactivation sequence
5.9
VCC Generator
The VCC generator has a capacity to supply up to 80 mA continuously at 5V and 65 mA at 3V. An internal overload detector operates at approximately 120 mA. Current samples to the detector are internally filtered, allowing spurious current pulses up to 200 mA with a duration in the order of s to be drawn by the card without causing deactivation. The average current
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Functional description
ST8024
must stay below the specified maximum current value. For reasons of VCC voltage accuracy, a 100 nF capacitor with an ESR < 100 m should be tied to CGND near to pin VCC, and 100 nF capacitor with the same ESR should be tied to CGND near card reader contact C1.
5.10
Fault detection
The following fault conditions are monitored: - Short-circuit or high current on VCC - Removal of a card during a transaction - VDD dropping - DC/DC converter operating out of the specified values (VDDP too low or current from VUP too high) - Overheating. - There are two different cases (see Figure 8.): - CMDVCC HIGH outside a card session. Output OFF is LOW if a card is not in the card reader, and HIGH if a card is in the reader. A voltage drop on the VDD supply is detected by the supply supervisor, this generates an internal Power-on reset pulse but does not act upon OFF. No short-circuit or overheating is detected because the card is not powered-up. - CMDVCC LOW within a card session. Output OFF goes LOW when a fault condition is detected. As soon as this occurs, an emergency deactivation is performed automatically (see Figure 9.). When the system controller resets CMDVCC to HIGH it may sense the OFF level again after completing the deactivation sequence. This distinguishes between a hardware problem or a card extraction (OFF goes HIGH again if a card is present). Depending on the type of card-present switch within the connector (normally-closed or normally-open) and on the mechanical characteristics of the switch, bouncing may occur on the PRES signals at card insertion or withdrawal. There is a debounce feature in the device with an 8 ms typical duration (see Fig.8). When a card is inserted, output OFF goes HIGH only at the end of the debounce time. When the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on PRES or PRES and output OFF goes LOW. Figure 8. Behavior of OFF, CMDVCC, PRES and VCC
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ST8024
Functional description
Figure 9.
Emergency deactivation sequence (card extraction)
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Application
ST8024
6
Application
Figure 10. Application diagram
(1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm). (2) ST8024 and the microcontroller must use the same VDD supply. (3) Make short, straight connections between CGND, C5 and the ground connection to the capacitor. (4) Mount one low ESR-type 100 nF capacitor close to pin VCC. (5) Mount one low ESR-type 100 nF capacitor close to C1 contact. (6) The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by grounded tracks. (7) Optional resistor bridge for changing the threshold of VDD. If this bridge is not required pin 18 should be connected to ground.
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ST8024
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
ST8024
SO-28 MECHANICAL DATA
mm. DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.40 0.50 17.70 10.00 1.27 16.51 7.60 1.27 0.291 0.020 18.10 10.65 0.1 0.35 0.23 0.5 45 (typ.) 0.697 0.393 0.050 0.650 0.300 0.050 0.713 0.419 TYP MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. TYP. MAX. 0.104 0.012 0.019 0.012 inch
8 (max.)
0016023
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ST8024
Package mechanical data
TSSOP28 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 9.6 6.2 4.3 9.7 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 9.8 6.6 4.48 0.002 0.031 0.007 0.004 0.378 0.244 0.169 0.382 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.386 0.260 0.176 inch
0128292B
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Package mechanical data
ST8024
Tape & Reel SO-28 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 10.8 18.2 2.9 3.9 11.9 12.8 20.2 60 30.4 11.0 18.4 3.1 4.1 12.1 0.425 0.716 0.114 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.433 0.724 0.122 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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ST8024
Package mechanical data
Tape & Reel SO-28 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 10.8 18.2 2.9 3.9 11.9 12.8 20.2 60 30.4 11.0 18.4 3.1 4.1 12.1 0.425 0.716 0.114 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.433 0.724 0.122 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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Package mechanical data
ST8024
Tape & Reel TSSOP28 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.8 10.1 1.7 3.9 11.9 12.8 20.2 60 22.4 7 10.3 1.9 4.1 12.1 0.268 0.398 0.067 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.276 0.406 0.075 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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ST8024
Revision history
8
Table 22.
Date
Revision history
Revision history
Revision 4 5 6 Pag. 10, fig. 4, RSTIN ==> CLK. Add package TSSOP28 and new template. The comment point 5 on page 22 has been removed. Changes
18-Mar-2004 27-Jun-2006 13-Dec-2006
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ST8024
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